Semiconductor device and process for producing the same

ABSTRACT

A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.

TECHNICAL FIELD

The present invention relates to a semiconductor device and amanufacturing method therefor, and more particularly to a semiconductordevice and a manufacturing method therefor employing a high resistivitysilicon substrate, which is a power semiconductor device material.

BACKGROUND ART

The MCZ (magnetic field applied Czochralski) method and the FZ (floatingzone) method have been widely used to produce silicon wafers. Thesesilicon wafers are used to manufacture various semiconductor devices.

When such a silicon wafer is produced and used to manufacture asemiconductor device, the wafer is subjected to an oxidation diffusionprocess at an elevated temperature, which causes oxygen to enter intoand remain in the wafer as dissolved oxygen.

When the silicon substrate (or wafer) is heat treated at a lowtemperature during the semiconductor device manufacturing process, thedissolved oxygen forms thermal donors, thereby changing the resistivityof the silicon substrate. Therefore, it is desirable to reduce theamount of oxygen dissolved into the silicon substrate as much aspossible during the wafer production process and the semiconductordevice manufacturing process (see, e.g., Patent Document 1 below).

Patent Document 1: JP-A-2005-145744

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

Reducing the oxygen concentration of a silicon wafer as it is beingproduced requires an increase in the complexity and cost of theproduction process. A solution to this problem is a method ofmanufacturing a device structure on a silicon wafer in such a way thatthe device characteristics are good and exhibit little variation even ifthe wafer has a relatively high concentration of dissolved oxygen whenproduced (i.e., before the device manufacturing process).

The present invention has been devised to solve the above problems. Itis, therefore, an object of the present invention to manufacture adevice on a silicon wafer in such a way that the device characteristicsare good and exhibit little variation even if the wafer has a relativelyhigh concentration of dissolved oxygen before the device manufacturingprocess.

Means for Solving the Problems

A semiconductor device of the present invention comprises: a siliconsubstrate having a first surface and a second surface and formed by afloating zone method or a magnetic field applied Czochralski method; afirst conductive region provided in said first surface; and atrace-bearing portion provided in said second surface and including atrace of removal of at least a portion of a gettering layer forgettering dissolved oxygen or residual metal in said silicon substrate.

A method for manufacturing a semiconductor device of the presentinvention, comprises the steps of: forming a gettering layer on a secondsurface of a silicon substrate formed by a floating zone method or amagnetic field applied Czochralski method, wherein said siliconsubstrate further has a first surface, and wherein said gettering layerserves to getter dissolved oxygen or residual metal in said siliconsubstrate; heat treating said silicon substrate; removing at least aportion of said gettering layer.

EFFECT OF THE INVENTION

Thus, the present invention allows a device to be manufactured on asilicon wafer in such a way that the device characteristics are good andexhibit little variation even if the wafer has a relatively highconcentration of dissolved oxygen.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 Figure shows a manufacturing method for a semiconductor deviceaccording to a first embodiment.

FIG. 2 Figure shows the gettering of heavy metals and dissolved oxygen.

FIG. 3 Figure shows a manufacturing method for a semiconductor deviceaccording to a second embodiment.

FIG. 4 Figure shows a manufacturing method for a semiconductor deviceaccording to a third embodiment.

FIG. 5 Figure shows a manufacturing method for a semiconductor deviceaccording to a fourth embodiment.

FIG. 6 Figure shows a manufacturing method for a semiconductor deviceaccording to a fifth embodiment.

FIG. 7 Figure shows a variation of a manufacturing method for asemiconductor device according to a fifth embodiment.

FIG. 8 Figure shows a variation of a semiconductor device according tothese embodiments.

FIG. 9 Figure shows a variation of a semiconductor device according tothese embodiments.

DESCRIPTION OF REFERENCE NUMERALS

-   1 silicon substrate-   3 a gettering layer-   5 gate-   6 metal wiring-   8 n-type buffer layer-   9 p-type collector layer-   10 heavy metal-   11 dissolved oxygen-   12 wafer-   14 anode electrode-   15 cathode electrode-   16 n-type impurity layer

BEST MODES FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention will now be describedwith reference to the accompanying drawings. It should be noted that inthe figures, like numerals are used to denote like or correspondingcomponents to simplify the description and avoid undue repetition.

First Embodiment

There will now be described, with reference to FIG. 1, a semiconductordevice and a manufacturing method therefor according to a firstembodiment of the present invention. This semiconductor device ismanufactured from a silicon substrate (or silicon wafer) produced by thefloating zone (FZ) method or the magnetic field applied Czochralski(MCZ) method.

The silicon substrate has a first surface (or first principal surface)and a second surface (or second principal surface), and a device such asa transistor is formed on the first principal surface side of thesubstrate by a device manufacturing process. This silicon substrate isdoped with an n-type impurity and contains a predetermined concentrationof dissolved oxygen.

First, a silicon oxide film 2 is formed on the first principal surfaceof the silicon substrate 1, as shown in FIG. 1( a). Next, phosphorus isdiffused into the second principal surface of the silicon substrate 1 toform a high concentration impurity layer 3, as shown in FIG. 1( b). Thisimpurity layer is then heat treated to form a gettering layer 3 a overthe second principal surface of the silicon substrate 1, as shown inFIG. 1( c). The gettering layer 3 a can getter dissolved oxygen orresidual metal in the silicon substrate 1, as described later.

One method of diffusing phosphorus as described above is to usephosphine (PH₃) as a source gas. Another method is to use vapor ofliquid phosphorus oxychloride (POCl₃). Still another method is to placethe silicon substrate 1 and solid boron phosphide (BP) in a diffusionfurnace.

It should be noted that the impurity layer 3 may be formed by phosphorusion implantation. The formation of the impurity layer 3 by phosphorusdiffusion or phosphorus ion implantation allows the gettering layer 3 ato have the desired concentration profile.

The gettering layer containing phosphorus as an impurity will now bedescribed. When a silicon substrate containing phosphorus is oxidized,regions of the substrate containing a high phosphorus concentration areoxidized at a higher rate than those containing no phosphorus. If thephosphorus-containing regions have a phosphorus concentration of 1×10¹⁸atoms/cm² or more, they will undergo enhanced oxidation, that is, theiroxidation rate will be 3 to 5 times higher than those of the otherregions, although this may vary depending on the oxidation conditions.Further, the oxidation rate of these phosphorus-containing regions maybe one or more orders of magnitude higher than those of the otherregions if they contain a phosphorus concentration of 1×10¹⁹ atoms/cm²or more.

When such enhanced oxidation occurs, most of the oxygen supply foroxidizing the silicon substrate is externally delivered. However, someof the dissolved oxygen in the silicon substrate is also consumed atthat time. That is, if enhanced oxidation occurs in the siliconsubstrate after the gettering layer 3 a is formed therein, the getteringlayer 3 a getters dissolved oxygen in the substrate.

A silicon oxide film includes approximately 5×10²² atoms per cubiccentimeter (atoms/cm³). These atoms include approximately 1.5×10²²oxygen atoms. Therefore, the formation of a silicon oxide film having athickness of 1 μm (or 1×10⁻⁴ cm) consumes an amount of oxygen equivalentto a dose amount of approximately 1.5×10¹⁸ atoms/cm² (i.e., 1.5×10²²atoms/cm³×1×10⁻⁴ cm=1.5×10¹⁸ atoms/cm²).

In the above enhanced oxidation, if 1 to 10% of the oxygen used tooxidize the silicon substrate comes from the dissolved oxygen in thesubstrate, the amount of dissolved oxygen consumed is equivalent to adose amount of 1.5×10¹⁶ to 1.5×10¹⁷ atoms/cm². If the silicon substratehas a thickness of 100 μm (or 1×10⁻² cm), the gettering layer getters1.5×10¹⁸ to 1.5×10¹⁹ dissolved oxygen atoms per cubic centimeter volumeof the substrate (atoms/cm³), (i.e., 1.5×10¹⁶ to 1.5×10¹⁷atoms/cm²/1×10⁻² cm=1.5×10¹⁸ to 1.5×10¹⁹ atoms/cm³).

Although the gettering layer 3 a has been described as containingphosphorus as an impurity, it is to be understood that other n-typeimpurities such as arsenic or antimony may be substituted therefor, orp-type impurities such as silicon, aluminum, or gallium may besubstituted. Further, the gettering layer 3 a may contain as an impuritya Group IV element such as boron, germanium, or carbon, or a neutralelement such as argon or helium.

Therefore, one of the above impurities may be diffused in the siliconsubstrate 1 to form the gettering layer. Alternatively, the siliconsubstrate 1 may be ion-implanted with such an impurity and then heattreated to form the gettering layer.

Next, a p-type diffusion layer 4 (or first conductive region) is formedon the first principal surface of the silicon substrate 1, as shown inFIG. 1( d). This is accomplished by a thermal diffusion process. At thattime, if enhanced oxidation occurs in the silicon substrate 1, thegettering layer 3 a getters dissolved oxygen in the substrate, therebyreducing the concentration of dissolved oxygen in the silicon substrate1.

Thus, the gettering layer 3 a is formed on the second principal surfaceof the silicon substrate 1, and then the substrate is heat treated togetter dissolved oxygen therein. As a result, the gettering layer 3 agetters dissolved oxygen contained in the silicon substrate 1, resultingin a reduction in the concentration of dissolved oxygen of the substrate1. Further, not only can the gettering layer 3 a getter dissolved oxygenin the silicon substrate 1, but also it can getter residual metal in thesubstrate 1.

Next, a trench gate structure, e.g., including gates 5 (or firstelectrodes) of insulated gate bipolar transistors (hereinafter referredto as “IGBTs”) is formed in the first principal surface of the siliconsubstrate 1, as shown in FIG. 1( d). Metal wiring 6 of Al, etc. is thenformed over the first principal surface of the silicon substrate 1. Itshould be noted that heavy metals such as Fe may undesirably diffuse inthe silicon substrate 1 during the wafer production process at the wafermanufacturer's site or during the device manufacturing process. This mayoccur accidentally or due to the fact that materials used to form thewafer or devices are of low purity. Such metals nucleate crystal defectsin the silicon substrate 1 or create carrier trap states in thesemiconductor bandgap, thereby degrading the device characteristics.

As described above, the gettering layer 3 a contains phosphorus, whichhas the property of causing metal to agglomerate by diffusion transportin a solid. Therefore, the gettering layer 3 a can getter heavy metalssuch as Fe present in the silicon substrate 1 even when they aredistributed throughout the substrate. This prevents a reduction in thelifetime of the current carriers (holes and electrons) in the siliconsubstrate 1, as well as reducing the leakage current flowing when avoltage is applied to the device.

Next, referring to FIG. 1( e), the second principal surface of thesilicon substrate 1 is mechanically ground to remove the portion of thesubstrate 1 below the broken line 7. This results in the removal of theentire gettering layer 3 a, producing the structure shown in FIG. 1( f).It should be noted that the gettering layer 3 a may be removed by achemical process such as dry or wet etching. The removal of thegettering layer 3 a leaves a trace-bearing portion (not shown) bearingtraces of the removal on the second principal surface side of thesilicon substrate 1.

The removal of the gettering layer 3 a allows reduction of theconcentrations of heavy metals and dissolved oxygen in the siliconsubstrate 1, thereby limiting the increase in the junction leakagecurrent due to the presence of the heavy metals in the silicon substrate1. Further, it is also possible to limit the variation in theresistivity of the silicon substrate 1 due to the dissolved oxygen.

Next, as shown in FIG. 1( g), an n-type buffer layer 8 containing ann-type impurity is formed over the second principal surface of thesilicon substrate 1, thereby covering the trace-bearing portion bearingtraces of the removal of the gettering layer 3 a. For example, then-type buffer layer 8 is formed by means of phosphorus ion implantationand heat treatment. A p-type collector layer 9 (or second conductiveregion) containing a p-type impurity is then formed to cover the n-typebuffer layer 8. For example, the p-type collector layer 9 is formed bymeans of boron ion implantation and heat treatment.

Thus, according to the present embodiment, first the gettering layer 3 ais formed on the silicon substrate 1, which is then heat treated tocause the gettering layer 3 a to getter dissolved oxygen and residualmetals in the substrate 1. Next, the metal wiring (aluminum wiring) 6 isformed, and the gettering layer 3 a is removed. Then the secondconductive region (or p-type collector layer 9) is formed.

That is, according to the present embodiment, the step of forming themetal wiring 6 on the first principal surface of the semiconductorsubstrate 1 is performed after the step of heat treating the siliconsubstrate 1 and before the step of removing the gettering layer 3 a.Further, the second conductive region is formed in the second principalsurface side of the silicon substrate 1 after the step of removing thegettering layer 3 a. Specifically, the second conductive region formingstep first forms an impurity layer on the second principal surface sideof the silicon substrate 1 by ion implantation, etc., and then heattreats the substrate at a temperature (300 to 450° C.) lower than themelting point of the metal wiring (or aluminum wiring) 6 to activate theimpurity layer.

Thus, the manufacturing method described above allows the manufacture ofa semiconductor device including: a silicon substrate 1 having a firstsurface (or first principal surface) and a second surface (or secondprincipal surface) and formed by the FZ or MCZ method; a firstconductive region (or p-type diffusion layer 4) provided in the firstprincipal surface; and a trace-bearing portion provided in the secondprincipal surface and including a trace of removal of at least a portionof a gettering layer for gettering dissolved oxygen or residual metal inthe silicon substrate 1.

The semiconductor device is further configured such that a secondconductive region (or p-type collector layer 9) is provided in thesecond principal surface so as to cover the trace-bearing portion. Thatis, the structure shown in FIG. 1( g) is a vertical device structuremade up of the first conductive region (or p-type diffusion layer 4),the silicon substrate 1, and the second conductive region (or p-typecollector layer 9).

The trace-bearing portion has a shorter carrier lifetime than the otherportions of the silicon substrate 1. More specifically, thetrace-bearing portion has a shorter carrier lifetime than the otherportions of the substrate 1 by a factor of 10 or more. Thistrace-bearing portion can be used as a control layer for locallycontrolling the carrier lifetime of the silicon substrate 1.

The gettering of heavy metals and dissolved oxygen by the getteringlayer 3 a will now be described with reference to FIG. 2. As shown inFIGS. 2( a) and 2(b), the gettering layer 3 a is formed on the secondprincipal surface of the silicon substrate 1 (the left surface in FIG.2( a)). When the silicon substrate 1 contains heavy metal 10, thegettering layer 3 a getters the metal by causing it to agglomerate bydiffusion transport, as shown in FIG. 2( a). Further, when enhancedoxidation occurs in the silicon substrate 1 due to the application of ahigh temperature diffusion process, etc., not only does the getteringlayer 3 a getter the heavy metal 10, but also dissolved oxygen in thesilicon substrate 1 segregates on the surface of the gettering layer 3a, as shown in FIG. 2( b). This results in the formation of a siliconoxide film 3 b over the surface of the gettering layer 3 a. Thus, thegettering layer 3 a getters heavy metals and dissolved oxygen present inthe silicon substrate.

As described above, the present embodiment eliminates the need togreatly reduce the concentration of dissolved oxygen in a wafer beforeforming a device on the wafer, resulting in reduced manufacturing cost.Further, the present embodiment allows the concentration of dissolvedoxygen in a silicon substrate to be adjusted in the device manufacturingprocess, thereby increasing the flexibility of the application of thesilicon substrate. That is, the present embodiment allows a device to bemanufactured on a silicon wafer in such a way that the devicecharacteristics are good and meet the requirements of the applicationand exhibit little variation even if the wafer has a relatively highconcentration of dissolved oxygen before the device manufacturingprocess.

In the present embodiment, the gettering layer 3 a is formed in thesilicon substrate at the beginning of the device manufacturing process.In other embodiments, however, the gettering layer 3 a may be formedbefore the device manufacturing process and may be removed after itgetters dissolved oxygen in the silicon substrate. This allows theconcentration of dissolved oxygen in the substrate to be reduced beforethe device manufacturing process.

Further, in the present embodiment, the gates 5 having a trench gatestructure are formed on the first principal surface side of the siliconsubstrate 1, and the LPT (light punch through) structure including then-type buffer layer 8 and the p-type collector layer 9 is formed on thesecond principal surface side of the silicon substrate 1. It is to beunderstood, however, that in other embodiments the LPT structure may bereplaced by an FS (field stop) structure or an SPT (soft punch through)structure, which are similar to the LPT structure. Further, although inthe present embodiment the trench gate structure shown in FIG. 1 isformed on the first principal surface side of the silicon substrate 1,it is to be understood that the trench gate structure may be replaced byone of the following structures: an IEGT (injection enhanced gatetransistor), a planar gate structure, a MOS gate structure, a “junctiontype” thyristor, a GTO (gate turn-off) thyristor, a GCT (gate commutatedturn-off), an SITh (static induction thyristor), and a simple diodestructure with no control electrode.

Further, although in the present embodiment phosphorus is used to formthe gettering layer 3 a, it is to be understood that in otherembodiments any other element may be substituted therefor which has theeffect of gettering heavy metal or dissolved oxygen, as described above.Further, although in the present embodiment the silicon substrate 1 isan n-type silicon substrate, it is to be understood that in otherembodiments the substrate may be a p-type silicon substrate and theconductivity types of the other layers or regions in this semiconductordevice may be reversed. Still further, the silicon substrate 1 may be asubstrate made of an intrinsic semiconductor (containing no n-type andp-type impurities).

Second Embodiment

There will now be described, with reference to FIG. 3, a method formanufacturing a semiconductor device according to a second embodiment ofthe present invention. The following description will be primarilydirected to the differences from the first embodiment. This methodbegins by performing the four steps shown in FIGS. 3( a) to 3(d) fromthe step of forming a silicon oxide film on a first principal surface ofa silicon substrate 1 to the step of forming metal wiring 6, as in thefirst embodiment.

Next, referring to FIG. 3( e), the second principal surface of thesilicon substrate 1 is mechanically ground to remove the portion of thesubstrate 1 below the broken line 7. That is, a portion of the getteringlayer 3 a is removed such that the remaining portion of the getteringlayer 3 a has a predetermined thickness, producing the structure shownin FIG. 3( f). This allows limiting the increase in the junction leakagecurrent due to the presence of heavy metals in the silicon substrate, asin the first embodiment. Further, it is also possible to limit thevariation in the resistivity of the silicon substrate 1 due to dissolvedoxygen in the substrate.

Next, as shown in FIG. 3( g), a p-type collector layer 9 containing ap-type impurity is formed over the second principal surface of thesilicon substrate 1, thereby covering the remaining portion of thegettering layer 3 a. For example, the p-type collector layer 9 is formedby first ion-implanting the second principal surface of the siliconsubstrate 1 with boron and then heat treating the substrate.

According to the present embodiment, a portion of the gettering layer 3a is removed such that the remaining portion of the gettering layer 3 ahas a predetermined thickness, as described above. On the other hand,according to the method of the first embodiment, the entire getteringlayer 3 a is removed. Thus, the second embodiment eliminates the step offorming the n-type buffer layer 8 described in connection with the firstembodiment, since, according to the method of the second embodiment,only a portion of the gettering layer 3 a is removed. That is, thesecond embodiment can reduce the total number of process steps ascompared to the first embodiment while retaining the advantages of thefirst embodiment.

Thus, the second embodiment can reduce the total number of process stepsas compared to the first embodiment while retaining the advantages ofthe first embodiment.

Third Embodiment

There will now be described, with reference to FIG. 4, a method formanufacturing a semiconductor device according to a third embodiment ofthe present invention. The following description will be primarilydirected to the differences from the first embodiment. It should benoted that, according to the method of the first embodiment, thegettering layer 3 a is removed after the metal wiring 6 is formed. Onthe other hand, according to the method of the present embodiment, themetal wiring 6 is formed after the gettering layer 3 a is removed andafter the n-type buffer layer 8 and the p-type collector layer 9 areformed.

For example, this method begins by performing the four steps shown inFIGS. 4( a) to 4(d) from the step of forming a silicon oxide film 2 on afirst principal surface of a silicon substrate 1 to the step of forminggates 5, as in the first embodiment. Then, referring to FIG. 4( e), thesecond principal surface of the silicon substrate 1 is mechanicallyground to remove the entire gettering layer 3 a, producing the structureshown in FIG. 4( f). An n-type buffer layer 8 and a p-type collectorlayer 9 are then sequentially formed on the second principal surface ofthe silicon substrate 1 by means of ion implantation and heat treatment.Further, metal wiring 6 of Al, etc. is formed over the gates 5.

In the above example, the entire gettering layer 3 a is removed beforethe n-type buffer layer 8 and the p-type collector layer 9 are formed.However, as in the second embodiment, only a portion of the getteringlayer 3 a may be removed, and the p-type collector layer 9 may be formedto cover the remaining portion of the gettering layer 3 a. Then themetal wiring 6 may be formed.

That is, according to the present embodiment, the metal wiring 6 isformed on the first principal surface of the silicon substrate 1 afterthe gettering layer 3 a is removed and after the n-type buffer layer 8and the p-type collector layer 9 are formed on the second principalsurface of the silicon substrate 1. Alternatively, the metal wiring 6 isformed on the first principal surface of the silicon substrate 1 after aportion of the gettering layer 3 a is removed and after the p-typecollector layer 9 is formed on the second principal surface of thesilicon substrate 1. Thus, in both cases, the metal wiring 6 is formedafter the p-type collector layer 9 is formed, thereby avoiding asituation where the high temperature heat treatment used to form thep-type collector layer 9 affects the metal wiring 6. Therefore, thepresent embodiment allows the semiconductor device to have goodcharacteristics while retaining the advantages of the first and thesecond embodiments.

This manufacturing method can be used to form a high voltage IGBT (2500V or higher), etc. if a heat treatment can be applied to the siliconsubstrate before or after the formation of the contact holes, that is,if the silicon substrate has a sufficient thickness after the IGBTstructure is formed and after the second principal surface of thesilicon substrate is ground.

Thus, the present embodiment allows the semiconductor device to havegood characteristics while retaining the advantages of the first andsecond embodiments.

Fourth Embodiment

There will now be described, with reference to FIG. 5, a method formanufacturing a semiconductor device according to a fourth embodiment ofthe present invention. According to the first to third embodiments, adevice manufacturing process is performed on a silicon substrateproduced by the FZ or MCZ method. The present embodiment provides amethod for forming a gettering layer on one surface of a siliconsubstrate before the substrate is subjected to a device manufacturingprocess.

First, a silicon ingot formed by the FZ or MCZ method is cut to producea wafer 12 having a predetermined thickness, as shown in FIG. 5( a).This wafer has surfaces 14 a and 14 b. Next, phosphorus is diffused intothese surfaces to form an impurity layer 3 on each surface. Theseimpurity layers may be formed by phosphorus ion implantation, or bycoating phospho silicate glass (PSG).

The impurity layers 3 are then heat treated at an elevated temperatureto diffuse the impurity (phosphorus), with the result that a getteringlayer 3 a is formed on each of the surfaces 14 a and 14 b of the wafer12, as shown in FIG. 15( c). These gettering layers have the effect ofgettering heavy metals and dissolved oxygen, as in the first to thirdembodiments. It should be noted that the gettering layers are formedsuch that the amount of impurity does not exceed its solubility limit inthe silicon substrate.

Next, as shown in FIG. 5( d), the wafer 12 is split into two thinnerwafers by cutting along a plane perpendicular to the thickness directionof the wafer 12. Specifically, this step produces a wafer 12 a havingthe surface 14 a with a gettering layer 3 a thereon, and a wafer 14 bhaving the surface 14 b with another gettering layer 3 a thereon, asshown in FIG. 5( e). Then, the cut surfaces 14 c and 14 d are mirrorfinished. These surfaces 14 c and 14 d can be used as first principalsurfaces of silicon substrates on which MOS gate devices, etc. areformed.

Thus, the two wafers 12 a and 12 b have their respective getteringlayers 3 a which are simultaneously formed before these wafers areproduced by splitting as described above. That is, only half as manywafers need be subjected to a gettering layer formation process ascompared to the first to third embodiments.

Thus, the present embodiment provides a method for forming getteringlayers 3 a such as that described in connection with the first to thirdembodiments, the method including the steps of: forming a getteringlayer on each surface of a wafer having a predetermined thickness, thewafer having been produced by the FZ or MCZ method; and splitting thewafer along a plane perpendicular to the thickness direction of thewafer to produce two silicon substrates each having a gettering layer onone principal surface side thereof.

Next, though not shown, devices such as MOS gates, etc. are formed onthe surface 14 c (or first principal surface) of the wafer 12 a and onthe surface 14 d (or first principal surface) of the wafer 12 b, as inthe first to third embodiments. All the other components are the same asthose described in connection with the first to third embodiments.

It should be noted that a protective film such as a silicon oxide filmmay be formed on each of the surfaces 14 a and 14 b before the impuritylayer forming step described above (see FIG. 5( b)). Further, althoughin the present embodiment the gettering layers contain phosphorus as animpurity, it is to be understood that in other embodiments any othern-type impurity or any p-type impurity may be substituted therefor whichhas the effect of gettering heavy metal or dissolved oxygen.

Thus, the present embodiment allows a reduction in the number of wafersto be subjected to a gettering layer forming process resulting inreduced manufacturing cost while retaining the advantages of the firstto third embodiments.

Fifth Embodiment

There will now be described, with reference to FIG. 6, a method formanufacturing a semiconductor device, especially, a PIN (positiveintrinsic negative) diode. This method begins by performing the threesteps shown in FIGS. 6( a) to 6(c) from the step of forming a siliconoxide film 2 on a first principal surface of a silicon substrate 1 tothe step of forming a gettering layer 3 a on a second principal surfaceof the silicon substrate 1, as in the first embodiment (see FIGS. 1( a)to 1(c)). The gettering layer 3 a has the effect of gettering dissolvedoxygen or heavy metal in the silicon substrate, as in the first tofourth embodiments.

Next, the first principal surface of the silicon substrate 1 ision-implanted with boron to form a p-type impurity layer thereon. A heattreatment is then performed to form a p-type anode electrode 14 on thefirst principal surface of the silicon substrate 1, as shown in FIG. 6(d). Then, referring to FIG. 6( e), the second principal surface of thesilicon substrate 1 is mechanically ground to remove the portion of thesubstrate 1 below the broken line 7. This results in the removal of theentire gettering layer 3 a, producing the structure shown in FIG. 6( f).

Although according to the above method the entire gettering layer 3 a isremoved, only a portion of the gettering layer 3 a may be removed, as inthe second embodiment.

The removal of at least a portion of the gettering layer 3 a allows theremoval of dissolved oxygen or heavy metal from the silicon substrate 1,thereby providing advantages similar to those of the first to fourthembodiments.

Next, an n-type impurity layer is formed on the second principal surfaceof the silicon substrate 1, for example, by phosphorus ion implantation.The impurity layer is then heat treated to form an n-type cathodeelectrode 15 on the second principal surface of the silicon substrate 1,as shown in FIG. 6( g).

According to the present embodiment, first the gettering layer 3 a isformed on the second principal surface of the silicon substrate 1. Then,after removing the gettering layer 3 a, the n-type cathode electrode 15is formed on the second principal surface of the silicon substrate 1.This allows for t control, i.e., reducing the carrier lifetime of thecathode electrode 15 side when a device such as a high voltage diode isformed. This control corresponds to reducing the carrier lifetime of then-type buffer layer 8 of the IGBTs described in connection with thefirst to fourth embodiments. Specifically, the t control enables aregion of the silicon substrate to have a carrier lifetime that is oneor more orders of magnitude shorter than those of the other regions.

Thus, according to the manufacturing method described above, the p-typeanode electrode 14 is formed on the first principal surface of thesilicon substrate 1, and the n-type cathode electrode 15 is formed onthe second principal surface of the substrate 1. This structure is avertical diode structure made up of the anode electrode 14, the siliconsubstrate 1, and the cathode electrode 15.

The present embodiment allows a device such as a high voltage diode tobe formed in such a way that the carrier lifetime of the cathodeelectrode 15 side of the device is one or more orders of magnitudeshorter than that of the other side. That is, the present embodimentprovides local carrier lifetime control (t control) while retaining theadvantages of the first to fourth embodiments.

A variation of the present embodiment will be described with referenceto FIG. 7. While in the present embodiment the gettering layer 3 a isformed on the second principal surface of the silicon substrate 1 (seeFIG. 6), in this variation the gettering layer 3 a is formed on thefirst principal surface of the silicon substrate 1.

This method begins by forming a silicon oxide film 2 on a firstprincipal surface of a silicon substrate 1, as shown in FIG. 7( a). Ap-type impurity layer is then formed in the first principal surface ofthe silicon substrate 1, and the silicon oxide film 2 is removed,producing the structure shown in FIG. 7( b). Next, the impurity layer 3is heat treated to form a gettering layer 3 a on the first principalsurface of the silicon substrate 1, as shown in FIG. 7( c). The siliconsubstrate 1 is then heat treated to cause the gettering layer 3 a togetter dissolved oxygen and residual metal present in the siliconsubstrate 1.

Then, referring to FIG. 7( d), the portion of the silicon substrate 1above the broken line 7 is removed by grinding, etc. This results in theremoval of the gettering layer 3 a, producing the structure shown inFIG. 7( e). A p-type impurity layer is then formed on the firstprincipal surface of the silicon substrate 1 and heat treated to form ananode electrode 14, as shown in FIG. 7( f). At that time, a pn junctionhaving a breakdown voltage higher than a predetermined value is formedbetween the anode electrode 14 and the silicon substrate 1. Next, ann-type impurity layer is formed on the second principal surface of thesilicon substrate 1 and heat treated to form a cathode electrode. Thisproduces a vertical device structure made up of the anode electrode 14,the silicon substrate 1, and the cathode electrode 15. The main currentflows between the anode electrode 14 and the cathode electrode 15through the silicon substrate 1.

The manufacturing method of the above variation begins by providing asilicon substrate 1 having a first principal surface and a secondprincipal surface and produced by the FZ or MCZ method. A getteringlayer is then formed on the first principal surface of the siliconsubstrate 1 so as to be able to getter dissolved oxygen or residualmetal in the silicon substrate 1. Next, the silicon substrate 1 is heattreated to getter dissolved oxygen or residual metal present in thesilicon substrate 1. Then, after removing the gettering layer, a firstconductive region of a first conductivity type is formed in the firstprincipal surface of the silicon substrate 1, and a second conductiveregion of a second conductivity type is formed in the second principalsurface of the silicon substrate 1.

Thus, the manufacturing method described above allows the manufacture ofa semiconductor device including: a silicon substrate 1 having a firstprincipal surface and a second principal surface and formed by the FZ orMCZ method; a trace-bearing portion provided in the first principalsurface and including a trace of removal of a gettering layer forgettering dissolved oxygen or residual metal in the silicon substrate 1;a first conductive region of a first conductivity type provided in thefirst principal surface and covering the trace-bearing portion; and asecond conductive region of a second conductivity type provided in thesecond principal surface; wherein the main current passes between thefirst and second principal surfaces.

Although the present embodiment and a variation thereof have beendescribed as forming a PIN diode structure, it is to be understood that,like the first embodiment, they may be applied to semiconductor devicesin which a gate structure of an IGBT, etc. is formed on the firstprincipal surface of the silicon substrate 1.

The first to fifth embodiments have been described in connection withstructures in which a p-type diffusion layer 4 is provided on a firstprincipal surface of a silicon substrate 1 containing an n-typeimpurity. However, these embodiments may be applied to a variation ofthese structures, in which an n-type impurity layer 16 having a highern-type impurity concentration than the silicon substrate 1 is providedunder the p-type diffusion layer 4, as shown in FIG. 8. Further, theymay be applied to a structure in which the silicon substrate 1 has non-type buffer layer on its second principal surface side, as shown inFIG. 9.

1-15. (canceled)
 16. A semiconductor device comprising: a siliconsubstrate having a first surface and a second surface and formed by afloating zone method or a magnetic field applied Czochralski method; afirst conductive region provided in said first surface; and atrace-bearing portion provided in said second surface and including atrace of removal of at least a portion of a gettering layer forgettering dissolved oxygen or residual metal in said silicon substrate.17. The semiconductor device as claimed in claim 16, further comprising:a second conductive region provided in said second surface and coveringsaid trace-bearing portion; wherein said semiconductor device has avertical device structure made up of said first conductive region, saidsilicon substrate, and said second conductive region.
 18. Thesemiconductor device as claimed in claim 16, wherein said getteringlayer contains an n-type impurity or a p-type impurity.
 19. Thesemiconductor device as claimed in claim 16, wherein said getteringlayer contains a Group IV element or a neutral element.
 20. Thesemiconductor device as claimed in claim 16, wherein said trace-bearingportion has a shorter carrier lifetime than the other portions of saidsilicon substrate.
 21. The semiconductor device as claimed in claim 20,wherein said trace-bearing portion has a shorter carrier lifetime thanthe other portions of said silicon substrate by a factor of 10 or more.22. A method for manufacturing a semiconductor device, comprising:forming a gettering layer on a second surface of a silicon substrateformed by a floating zone method or a magnetic field applied Czochralskimethod, wherein said silicon substrate has a first surface, and whereinsaid gettering layer serves to getter dissolved oxygen or residual metalin said silicon substrate; heat treating said silicon substrate; andremoving at least a portion of said gettering layer.
 23. The method asclaimed in claim 22, wherein said heat treating said silicon substrateis such that said gettering layer getters said dissolved oxygen in saidsilicon substrate.
 24. The method as claimed in claim 22, furthercomprising: forming metal wiring on said first surface after said heattreating said silicon substrate and before said removing at least aportion of said gettering layer; and forming a conductive region in saidsecond surface after said removing at least a portion of said getteringlayer.
 25. The method as claimed in claim 22, wherein said getteringlayer contains an n-type impurity or a p-type impurity.
 26. The methodas claimed in claim 22, wherein said gettering layer contains a Group IVelement or a neutral element.
 27. The method as claimed in claim 22,wherein said forming said gettering layer is effected by impuritydiffusion or ion implantation.
 28. The method as claimed in claim 22,wherein said forming said gettering layer includes: forming a getteringlayer on each surface of a wafer having a predetermined thickness, saidwafer having been formed by the floating zone method or the magneticfield applied Czochralski method; and splitting said wafer into twohalves along a plane perpendicular to the thickness direction of saidwafer to produce said silicon substrate.
 29. A semiconductor devicecomprising: a silicon substrate having a first surface and a secondsurface and formed by a floating zone method or a magnetic field appliedCzochralski method; a trace-bearing portion provided in said firstsurface and including a trace of removal of a gettering layer forgettering dissolved oxygen or residual metal in said silicon substrate;a first conductive region of a first conductivity type provided in saidfirst surface and covering said trace-bearing portion; and a secondconductive region of a second conductivity type provided in said secondsurface; wherein a main current passes between said first and secondsurfaces.
 30. A method for manufacturing a semiconductor device,comprising: forming a getting layer on a first surface of a siliconsubstrate formed by a floating zone method or a magnetic field appliedCzochralski method, wherein said silicon substrate has a second surface,and wherein said gettering layer serves to getter dissolved oxygen ordissolved metal in said silicon substrate; heat treating said siliconsubstrate to getter said dissolved oxygen or said residual metal in saidsilicon substrate; removing said gettering layer; forming a firstconductive region of a first conductivity type in said first surface ofsaid silicon substrate; and forming a second conductive region of asecond conductivity type in said second surface of said siliconsubstrate.